symbol, description, value, units, type
L_s,Source inductance,3/25,H,performance
R_s,Source resistance,875,Omega,performance
R_t,Termination resistance,10000,Omega,performance
Vi_pp,Maximum peak-peak input voltage,293171166286743/1000000000000000,,performance
f_fp,Maximum full-power frequency,5000,Hz,performance
tau_i,Integration time constant,1/62500,s,performance
f_min,-3dB high-pass cut-off frequency,600,Hz,performance
f_max,-3dB low-pass cut-off frequency,6000,Hz,performance
V_onoise,DIN A weighted output voltage noise,10617688884619767/1000000000000000000000,V,performance
Vi_ADC,Peak-peak input voltage ADC,9/10,V,performance
P_max,Maximum power dissipation at maximum supply voltage,1/1000,W,performance
V_DD,Maximum supply voltage,13/10,V,performance
SRCnoise,DIN A weighted RMS output noise&#44; source + termination,3141835556678589/2000000000000000000000,V,design
n_SRC,Relative contribution of source noise to the squared DIN-A weighted RMS output noise,109450291465331/5000000000000000,,budgets
n_Ri,Relative contribution of R_i noise to the squared DIN-A weighted RMS output noise,1/5,,budgets
Ri_max,Max. value of integrator resistor,894482844616127/100000000000,Omega,design
R_i,Selected value of integrator resistor,8900,Omega,design
Ri_min,Min. value of integrator resistor,3380,Omega,design
C_i,Required value of integrator capacitor,44943820224719/25000000000000000000000,F,design
I_fb,Maximum peak-peak current through feedback network,454156389523329/10000000000000000000,A,design
S_Ri,Squared DIN A weighted RMS output noise due to source and feedback network,24905098080013813/1000000000000000000000000000,V**2/Hz,design
n_Ri_obtained,Relative contribution of source and feedback network to squared DIN A weighted output noise,99513249090521/500000000000000,,design
n_MN,Relative contribution controller NMOS input stagenoise to the squared DIN-A weighted RMS output noise,1/2,,budgets
c_issN,Selected input capacitance NMOS,6911881223132911/1000000000000000000000000000,F,design
g_mN,Selected transconductance input stage NMOS,392717005280817/5000000000000000000,S,design
g_m_minN,Minimum transconductance input stage NMOS,392614357533391/10000000000000000000,S,design
c_iss_g_m_minN,Required c_issN at g_m_minN,9870464855257289/10000000000000000000000000,F,design
c_iss_costs_minN,Required c_iss NMOS for minimum costs,6911881223132911/1000000000000000000000000000,F,design
g_m_costs_minN,g_m NMOS for minimum costs,392717005280817/5000000000000000000,S,design
V_onoise_gmCissN,DIN A weighted RMS output noise with NMOS and selected g_m and c_iss,112761046236379/12500000000000000000,V,achievements
n_MP,Relative contribution controller PMOS input stagenoise to the squared DIN-A weighted RMS output noise,1/2,,budgets
c_issP,Selected input capacitance PMOS,6024334401490099/250000000000000000000000000000,F,design
g_mP,Selected transconductance input stage PMOS,376839503206833/5000000000000000000,S,design
g_m_minP,Minimum transconductance input stage PMOS,95662877010489/2500000000000000000,S,design
c_iss_g_m_minP,Required c_issN at g_m_minP,8736249358841839/10000000000000000000000000,F,design
c_iss_costs_minP,Required c_iss PMOS for minimum costs,6024334401490099/250000000000000000000000000000,F,design
g_m_costs_minP,g_m PMOS for minimum costs,376839503206833/5000000000000000000,S,design
V_onoise_gmCissP,DIN A weighted RMS output noise with PMOS and selected g_m and c_iss,180389823054317/20000000000000000000,V,achievements
W_N,Selected width input stage NMOS,47/20000,m,design
L_N,Selected length input stage NMOS,1/1000000,m,design
g_m_N_o,Obtained transconductance input stage NMOS,78543450492663/1000000000000000000,S,design
c_iss_N_o,Obtained input capacitance input stage NMOS,86094957532409/12500000000000000000000000,F,design
ID_N,Operating current input stage NMOS,282754370956489/100000000000000000000,A,design
IC_N,Inversion coefficient input stage NMOS,116673988882267/100000000000000000,,design
M_N,Number of fingers input stage NMOS,47,,design
W_F_N,Finger width input stage NMOS,12499999999999999/250000000000000000000,m,design
V_onoise_WLI_N,DIN A weighted RMS output noise with NMOS&#44; W&#44; L&#44; and ID,195834068730551/25000000000000000000,V,achievements
W_P,Selected width input stage PMOS,123094023552449/12500000000000000000,m,design
L_P,Selected length input stage PMOS,1/2500000,m,design
g_m_P_o,Obtained transconductance input stage PMOS,753500198330803/10000000000000000000,S,design
c_iss_P_o,Obtained input capacitance input stage PMOS,240999205836707/10000000000000000000000000000,F,design
ID_P,Operating current input stage PMOS,-27252670340339/6250000000000000000,A,design
IC_P,Inversion coefficient input stage PMOS,119683250013479/100000000000000,,design
M_P,Number of fingers input stage PMOS,1,,design
W_F_P,Finger width input stage PMOS,9999999999999999/1000000000000000000000,m,design
V_onoise_WLI_P,DIN A weighted RMS output noise with PMOS&#44; W&#44; L&#44; and ID,993220097859901/100000000000000000000,V,achievements
