17-12-2024: Design of accuracy, weak nonlinearity and bandwidth#
Lecture: EE4109-11
Location: Pulse Hall 7 (33.A2.200)
Time: 15:45 - 17:30
Design considerations#
The midband (or DC) accuracy, the bandwidth and the linearity of a feedback amplifier can all be increased by increasing the loopgain:
The midband (or DC) inaccuracy with respect to the asympotic gain equals the midband (or DC) inaccuracy of the servo function. It can be decreased by increasing the midband (or DC) loop gain.
The bandwidth of a negative feedback amplifier is defined as the bandwidth of the servo function, which models the frequency dependency with respect to the asymptotic gain. The bandwidth of the servo function is determined by its loop gain-poles product, considering only dominant poles.
The differential gain error with respect to the asymptotic gain equals that of the servo function. This, in turn, can be approximated by the ratio of the differential gain error of the loop gain and the midband (or DC) loop gain.
Type of stages#
T1 matrix parameters of stages should be as small as possible (nullor-like)
Considering the midband (or DC) accuracy:
Stages that maximally contribute to the midband (or DC) loop gain: cascode stages or their balanced version.
Considering the bandwidth:
Stages that maximally contribute to the loop gain-poles product: cascode stages or their balanced version.
Considering the bandwidth:
Stages that minimally contribute to the differential error to gain ratio: cascode stages or their balanced version.
Number of stages#
Considering the midband (or DC) accuracy:
No upper limit exists. Small-signal models can be used to evaluate the midband (or DC) loop gain. The DC loop gain can be increased through addition of stages or through positive feedback with loop gain less than unity.
Considering the bandwidth:
A cascode stage can add maximally \(f_T\) to the loop gain-poles product. Hence, the bandwidth of a negative feedback amplifier can never exceed \(f_T\). The number of stages is limited by the number of dominant poles that can be handled considering stability and frequency compensation.
Considering the weak nonlinearity:
No upper limit exists. The weak nonlinearity can only be checked with numeric (SPICE) simulations. The linearity can be improved by reducing the relative signal excursions (increase bias currents and voltages), through application of compensation techniques (reduction of even nonlinearity: balancing), or by adding more stages.
Biasing and interconnection considerations#
Considering the midband (or DC) accuracy and the bandwidth
Bias current sources insert finite inpedances in parallel with the signal path
Bias voltage sources insert finite inpedances in series with the signal path
Interconnection introduces capacitances in parallel with the signal path (and cross-talk) and resistance in series with the signal path.
Considering the weak nonlinearity
Bias current sources show the desired current source behavior over a limited voltage range.
Bias voltage sources show the desired voltage source behavior over a limited current range.
Group exersise#
Design a controller for the hearing loop receiver that has an adequate noise performance and drive capability and that provides a sufficiently large accuray, bandwidth and linearity.
Design the feedback network from the transfer and the noise requirements.
Evaluate the signal handling requirements at the input port and the output port of the amplifier.
Check if the noise performance and the signal handling requirements can be met with a single-stage controller.
If so, check the accuracy and the bandwidth of such a single-stage solution. If both are OK:
If necessary, apply frequency compensation.
Design a simple biased circuit that can be used for verification of the linearity of this single-stage solution.
If a single-stage controller is not possible, design a two-stage solution:
Design the type, the device geometry and the operating conditions of both stages considering noise and signal handling requirements of the amplifier.
Check the bandwidth and the accuracy, if both are OK:
If necessary, apply frequency compensation.
Design a simple biased circuit that can be used for verification of the linearity of this single-stage solution.
Our solution so far#
Please download the SLiCAP zip archive of the hearing loop design
Just another design problem#
A voltage amplifier must raise the level of its input signal to the peak peak input voltage range of an ADC. The following requirements apply when the amplifier is driven from a signal with a source resistance of 50 \(\Omega\) :
The noise figure should be better than 1.5 dB
The -3dB frequency range should be from 9 kHz to 30 MHz
The dynamic range should be at least 94 dB
Signals with crest factors up to 3 should be processed without clipping
The ADC input voltage range is 5 V
The ADC input impedance is 100 \(\Omega\)
The mean power consumption must be less than 15 mW
Give your remarks on the feasibility of this amplifier.