10-12-2024: Design of noise performance#
Lecture: EE4109-9
Location: Pulse Hall 7 (33.A2.200)
Time: 15:45 - 17:30
Design considerations noise performance#
A systems engineering approach to the design of the noise performance. In a top-down design approach we split error budgets, given as design input over the error contributers of sub circuits assigned during that design step.
Top-down noise budget distribution#
During the first design step, we design the feedback structure of the amplifier that performs the source-to-load signal transfer with the performance-to-costs ratio. At this top-level we have three noise contributers:
The signal source
The noise associated with the signal source should be known at the start of the design. Hence, this sub-budget is not free to select.
The feedback network
If the feedback network comprises passive elements, it contributes noise. A sub-budget must be assigned for this contribution. It sets a limit to the values of the feedback elements. The opposite limit (upper/lower) is found from the budget for the power dissipation in the feedback elements. In passive feedback amplifiers, there may exist a conflict of specifications (show-stopper) for noise and power dissipation.
Noise design equations for the feedback elements can be found using an amplifier model with noisy feedback elements and nullors as controllers.
The controller
The noisy controller can be modeled as a nullor with added equivalent-input noise sources. The input-referred voltage noise source and the input-referred current noise source have their associated transfer to the output. This transfer depends on the amplifier gain and on the values of the elements of the feedback network.
In many cases it is not very useful to specify individual design limits for the voltage noise and for the current noise source. This is because both sources can be partially correlated.
There exist multiple contributers to these input-referred noise sources and sub-budgets have to be assigned to them.
Noise of the signal path
Noise of the signal path consists of:
Noise of the input stage
If the input stage is a nullor-like stage (CS stage, anti-series CS stage or complementary-parallel CS stage) the noise of subsequent stages is not dominant. Hence the largest sub-sub-sub-budget at this hierarchical level is assigned to contribition of the input stage of the controller to the output noise of the amplifier.
Noise of subsequent stages
The noise contribution of subsequent stages should nor be dominant. Hence, a minor sub-sub-budget can be assigend to it.
Noise of the biasing
Like the subsequent stages, noise of the biasing should not be dominant. A minor sub-sub-budget can be assigend to it.
Noise of the biasing consists of:
Noise transferred from the power supply (PSRR)
The function of the biasing is to provide sufficiently accurate defined operating conditions for the signal path of the amplifier over the specified range of the power supply. Hence, the conversion from power supply variations to signal variations should be low enough (PSRR). If this is not possible, power supply filtering may be an option. A sub-sub-budget must be assigned for the transfer of power supply noise to the output signal.
Noise of the bias sources
As stated before, noise of the biasing circuitry should not be dominant. A minor sub-sub-budget can be assigend to it.
Group exersise#
Noise budgeting and design of input stage of hearing loop receiver.
Design a feedback structure for the hearing loop receiver.
Create a model of the hearing loop amplifier that can be used for determination of the values of the feedback elements considering their contribution to the output noise.
Assign values to the elements of the feedback network such that the contribution of the feedback to the output voltage variance is maximally 20% of the total budget.
Find values for the transconductance \(g_m\) and the input capacitance \(c_{iss}\), so that the contribution to the output voltage variance is maximally 60% of the total budget.
Estimate values for the channel width, the channel length and the DC operating current of an NMOS input CS stage from the obtained values of \(g_m\) and \(c_{iss}\).